2022-11-20 23:43:34 +00:00
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SAVMSC = $58
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2022-12-08 04:37:52 +00:00
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VDSLST = $200
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VDSLSTL = $200
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VDSLSTH = $201
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2022-11-25 19:51:27 +00:00
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COLPF0 = $D016
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COLPF1 = $D017
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COLPF2 = $D018
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COLPF3 = $D019
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COLBK = $D01A
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2022-11-30 07:59:38 +00:00
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AUDC1 = $D201
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2022-11-29 20:59:26 +00:00
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DMACTL = $D400
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2022-11-29 22:54:02 +00:00
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DLISTL = $D402
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DLISTH = $D403
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2022-11-25 19:51:27 +00:00
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WSYNC = $D40A
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VCOUNT = $D40B
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NMIEN = $D40E
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2022-11-26 16:48:01 +00:00
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temp1l = $80
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temp1h = $81
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temp1 = temp1l
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temp2l = $82
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temp2h = $83
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temp2 = temp2l
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2022-11-30 07:59:38 +00:00
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sample_ptrl = $84
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sample_ptrh = $85
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sample_ptr = sample_ptrl
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2022-11-30 11:04:31 +00:00
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scanline = $86
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2022-12-08 04:37:52 +00:00
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frame_counter = $89
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2022-11-26 16:48:01 +00:00
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2023-03-26 01:57:09 +00:00
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;height = 160
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height = 192
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2022-11-26 16:48:01 +00:00
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bytes_per_line = 40
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pages_per_frame = 32
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2022-11-30 07:59:38 +00:00
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lines_per_frame = 262
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2022-11-30 16:53:47 +00:00
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;scanline_offset = 31 + (40 - 24) / 2
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2023-03-26 03:19:27 +00:00
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scanline_offset = 30
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2022-11-30 11:04:31 +00:00
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scanline_max = (lines_per_frame - scanline_offset) / 2
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2022-11-26 16:48:01 +00:00
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2022-11-25 19:51:27 +00:00
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.data
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2022-12-08 02:20:24 +00:00
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.import frame1_top
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.import frame1_bottom
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2022-12-10 21:01:29 +00:00
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.import frame1_palette1_even
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.import frame1_palette1_odd
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.import frame1_palette2_even
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.import frame1_palette2_odd
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.import frame1_palette3_even
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.import frame1_palette3_odd
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2022-12-08 02:37:32 +00:00
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.import displaylist
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2022-12-08 01:11:22 +00:00
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2022-11-20 23:43:34 +00:00
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.code
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.export start
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.proc start
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2022-11-25 19:51:27 +00:00
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; Disable display DMA
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lda #$00
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2022-11-29 20:59:26 +00:00
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sta DMACTL
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2022-11-26 16:48:01 +00:00
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2022-11-29 22:54:02 +00:00
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; Disable VBI and DLI but allow Reset
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2022-12-08 02:20:24 +00:00
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lda #$20
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2022-11-29 22:54:02 +00:00
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sta NMIEN
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2022-11-25 19:51:27 +00:00
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; Set up the display list
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2022-11-26 01:35:10 +00:00
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lda #.lobyte(displaylist)
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2022-11-29 22:54:02 +00:00
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sta DLISTL
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2022-11-26 01:35:10 +00:00
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lda #.hibyte(displaylist)
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2022-11-29 22:54:02 +00:00
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sta DLISTH
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2022-11-25 19:51:27 +00:00
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2022-12-08 04:37:52 +00:00
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; Set up the DLI handler
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lda #.lobyte(dli_handler)
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sta VDSLSTL
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lda #.hibyte(dli_handler)
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sta VDSLSTH
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; Disable VBI but allow Reset and DLI
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lda #$a0
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sta NMIEN
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2022-11-25 19:51:27 +00:00
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; Manually wait for first scan line
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wait_vblank:
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2022-11-30 11:04:31 +00:00
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sta WSYNC
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2022-11-25 19:51:27 +00:00
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lda VCOUNT
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2022-11-26 01:35:10 +00:00
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bne wait_vblank
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2022-11-25 19:51:27 +00:00
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; Re-enable display DMA
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lda #$22
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2022-11-29 20:59:26 +00:00
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sta DMACTL
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2022-11-30 00:32:37 +00:00
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wait_start:
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2022-11-30 11:04:31 +00:00
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; Wait for the vblank
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; Resynchronize the scanline counter
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2022-11-30 07:59:38 +00:00
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wait_loop:
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2022-12-11 20:13:25 +00:00
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ldy VCOUNT ; 4 cycles
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bne wait_loop ; 2 cycles
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2022-11-26 03:17:34 +00:00
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2022-12-10 21:01:29 +00:00
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.macro inner_scanline frame_offset, line_offset
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; Y should be VCOUNT at entry
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2022-11-30 12:52:40 +00:00
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; it'll fire on unused lines, but harmlessly
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2022-12-10 21:01:29 +00:00
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;ldy scanline ; 3 cyc
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;inc scanline ; 5 cyc
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2022-11-30 11:04:31 +00:00
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2022-12-11 20:13:25 +00:00
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; 23-26 cycles before break
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2022-11-30 07:59:38 +00:00
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; Leisurely memory fetches
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2022-12-11 20:13:25 +00:00
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lda frame1_palette1_even + frame_offset + line_offset - scanline_offset / 2,y ; 4/5 @FIXME alternate
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pha ; 3
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ldx frame1_palette2_even + frame_offset + line_offset - scanline_offset / 2,y ; 4/5
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lda frame1_palette3_even + frame_offset + line_offset - scanline_offset / 2,y ; 4/5
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tay ; 2
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pla ; 3
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2022-11-30 07:59:38 +00:00
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; Wait for horizontal blank
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2022-12-11 20:13:25 +00:00
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sta WSYNC ; 4
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2022-11-30 07:59:38 +00:00
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2022-12-11 20:13:25 +00:00
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; 12 cycles after break
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2022-11-30 07:59:38 +00:00
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; Update color registers as fast as possible
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2022-12-11 20:13:25 +00:00
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sta COLPF0 ; 4
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stx COLPF1 ; 4
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sty COLPF2 ; 4
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2022-11-30 07:59:38 +00:00
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.endmacro
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2022-12-10 21:01:29 +00:00
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.macro run_frame frame_offset
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2022-12-08 04:37:52 +00:00
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.scope
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2022-12-12 00:37:47 +00:00
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; each scanline is 228 color clocks
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; that's 114 CPU cycles
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; minus 41-43 for DMA leaves 71-73 clock cycles per line
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2022-12-08 14:29:50 +00:00
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each_scanline_pair:
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2022-12-11 20:13:25 +00:00
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sty scanline ; 3 cycles
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inner_scanline frame_offset, 0 ; 23-26 cycles before break, 12 cycles after
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2022-12-10 21:01:29 +00:00
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2022-12-11 20:13:25 +00:00
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ldy scanline ; 3 cycles
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inner_scanline frame_offset, 128 ; 23-26 cycles before break, 12 cycles after
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2022-12-11 21:09:14 +00:00
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2022-12-12 00:37:47 +00:00
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; pair cleanup: 6 cycles
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2022-12-11 20:13:25 +00:00
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ldy VCOUNT ; 4 cycles
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bne each_scanline_pair ; 2 cycles
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2022-12-12 00:37:47 +00:00
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; frame cleanup: 11 cycles
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2022-12-11 20:13:25 +00:00
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lda frame_counter ; 3 cycles
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eor #1 ; 2 cycles
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sta frame_counter ; 3 cycles
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2022-12-12 01:46:56 +00:00
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;jmp wait_start ; 3 cycles
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jmp each_frame ; 3 cycles
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2022-12-08 04:37:52 +00:00
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.endscope
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.endmacro
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2022-11-26 03:17:34 +00:00
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2022-12-12 01:46:56 +00:00
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each_frame:
|
2022-12-08 14:29:50 +00:00
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run_frame1:
|
2022-12-10 21:01:29 +00:00
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run_frame 0
|
2022-11-25 19:51:27 +00:00
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|
2022-11-20 23:43:34 +00:00
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.endproc
|
2022-11-26 03:17:34 +00:00
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|
2022-12-08 04:37:52 +00:00
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.proc dli_handler
|
2022-12-08 13:59:09 +00:00
|
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lda #0
|
2022-12-08 04:37:52 +00:00
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sta frame_counter
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rti
|
2022-11-26 03:17:34 +00:00
|
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.endproc
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