347 lines
9.9 KiB
Rust
347 lines
9.9 KiB
Rust
use std::collections::HashMap;
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use std::vec::Vec;
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const PAGE_BITS: usize = 12;
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const PAGE_SIZE: usize = 2 << PAGE_BITS;
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// Actively used bits in our limited implementation:
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const BIT_V: u8 = 1;
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const BIT_R: u8 = 2;
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const BIT_W: u8 = 4;
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const BIT_X: u8 = 8;
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// (Not used) - user mode accessible
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const BIT_U: u8 = 16;
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/*
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// (Not used) - global mapping
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const BIT_G: u8 = 32;
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// (Not presently used) accessed -- set if we've touched this since last time A cleared
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const BIT_A: u8 = 64;
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// (Not presently used)dirty -- written since last time D cleared
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// Note each core/hart has its own dirty state for local JIT
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const BIT_D: u8 = 128;
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// (Not used or room for it) reserved for supervisor
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const BITS_RSW_LO: i64 = 256;
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const BITS_RSW_HI: i64 = 512;
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const BITS_RSW: i64 = BITS_RSW_LO | BITS_RSW_HI;
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*/
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#[repr(C)]
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#[derive(Clone, Copy)]
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struct PageTableEntry {
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flags: u8
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}
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impl PageTableEntry {
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fn new(flags: u8) -> Self {
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return Self {
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flags
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}
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}
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fn as_u8(&self) -> u8 {
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return self.flags;
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}
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fn is_valid(&self) -> bool {
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return self.flags & BIT_V == BIT_V;
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}
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fn is_readable(&self) -> bool {
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return self.flags & (BIT_V | BIT_R) == (BIT_V | BIT_R);
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}
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fn is_writable(&self) -> bool {
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return self.flags & (BIT_V | BIT_R | BIT_W) == (BIT_V | BIT_R | BIT_W);
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}
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fn is_executable(&self) -> bool {
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return self.flags & (BIT_V | BIT_R | BIT_X) == (BIT_V | BIT_R | BIT_X);
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}
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}
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type ExecutorFunc = fn(i64, &mut CoreState, &mut MachineState) -> i64;
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#[repr(C)]
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struct MachineState {
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memory: Vec<u8>,
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pages: Vec<PageTableEntry>,
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}
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/**
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* Note that physical memory accessors can traverse page boundaries;
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* we lay out linear memory from 0 to +4 gigabytes and will allocate
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* as many page table entries as are needed to cover RAM. These eat
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* up an extra 1 byte per 4 KiB of address space used (1 MiB per 4 GiB),
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* initially allocating enough for all physical memory allocated.
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*
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* This will be relatively space-inefficient for sparse address spaces
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* in the range of several gigabytes and more but requires only one
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* table lookup per load/store, or two if spanning pages.
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*
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* All threads in the process's machine will have access to the same
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* page tables, even if running on different threads.
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*/
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impl MachineState {
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fn new_with_state(memory: Vec<u8>, pages: Vec<PageTableEntry>) -> Self {
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if ((memory.len() >> PAGE_BITS) << PAGE_BITS) != memory.len() {
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panic!("memory size must be a multiple of 4096 bytes");
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}
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if ((memory.len() >> PAGE_BITS)) != pages.len() {
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panic!("page data is wrong length for memory size");
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}
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return Self {
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memory,
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pages
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};
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}
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fn new(memory_size: usize) -> Self {
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let memory = vec![0u8; memory_size];
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let pages = vec![PageTableEntry::new(0); memory_size >> PAGE_BITS];
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return Self::new_with_state(memory, pages);
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}
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fn get_page_table_entry(&mut self, address: usize) -> PageTableEntry {
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let page = address >> PAGE_BITS;
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if page < self.pages.len() {
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return self.pages[page];
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} else {
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return PageTableEntry::new(0);
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}
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}
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fn set_page_table_entry(&mut self, address: usize, entry: PageTableEntry) {
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let page = address >> PAGE_BITS;
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if page < self.pages.len() {
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self.pages[address >> 12] = entry;
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} else {
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panic!("@fixme: handle attempts to expand address space");
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}
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}
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fn lb_physical(&mut self, address: usize) -> i64 {
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return self.memory[address] as i8 as i64;
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}
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fn lbu_physical(&mut self, address: usize) -> i64 {
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return self.memory[address] as u8 as i64;
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}
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fn lh_physical(&mut self, address: usize) -> i64 {
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return (
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(self.memory[address ] as u16) |
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((self.memory[address + 1] as u16) << 8)
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) as i16 as i64;
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}
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fn lhu_physical(&mut self, address: usize) -> i64 {
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return (
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(self.memory[address ] as u16) |
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((self.memory[address + 1] as u16) << 8)
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) as i64;
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}
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fn lw_physical(&mut self, address: usize) -> i64 {
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return (
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(self.memory[address ] as u32) |
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((self.memory[address + 1] as u32) << 8) |
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((self.memory[address + 2] as u32) << 16) |
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((self.memory[address + 3] as u32) << 24)
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) as i32 as i64;
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}
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fn lwu_physical(&mut self, address: usize) -> i64 {
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return (
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(self.memory[address ] as u32) |
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((self.memory[address + 1] as u32) << 8) |
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((self.memory[address + 2] as u32) << 16) |
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((self.memory[address + 3] as u32) << 24)
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) as u32 as i64;
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}
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fn ld_physical(&mut self, address: usize) -> i64 {
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return (
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(self.memory[address ] as u64) |
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((self.memory[address + 1] as u64) << 8) |
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((self.memory[address + 2] as u64) << 16) |
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((self.memory[address + 3] as u64) << 24) |
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((self.memory[address + 4] as u64) << 32) |
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((self.memory[address + 5] as u64) << 40) |
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((self.memory[address + 6] as u64) << 48) |
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((self.memory[address + 7] as u64) << 56)
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) as i64;
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}
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fn sb_physical(&mut self, address: usize, value: i64) {
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self.memory[address] = value as u8;
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}
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fn sh_physical(&mut self, address: usize, value: i64) {
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self.memory[address] = value as u8;
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self.memory[address + 1] = (value >> 8) as u8;
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}
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fn sw_physical(&mut self, address: usize, value: i64) {
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self.memory[address] = value as u8;
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self.memory[address + 1] = (value >> 8) as u8;
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self.memory[address + 2] = (value >> 16) as u8;
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self.memory[address + 3] = (value >> 24) as u8;
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}
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fn sd_physical(&mut self, address: usize, value: i64) {
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self.memory[address] = value as u8;
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self.memory[address + 1] = (value >> 8) as u8;
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self.memory[address + 2] = (value >> 16) as u8;
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self.memory[address + 3] = (value >> 24) as u8;
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self.memory[address + 4] = (value >> 32) as u8;
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self.memory[address + 5] = (value >> 40) as u8;
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self.memory[address + 6] = (value >> 48) as u8;
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self.memory[address + 7] = (value >> 56) as u8;
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}
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fn store_buffer_physical(&mut self, address: usize, bytes: &[u8]) {
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self.memory[address..address + bytes.len()].copy_from_slice(bytes);
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}
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}
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#[repr(C)]
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struct CoreState {
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// Integer registers
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x: [i64; 32],
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// Do we need pc? we're passing it around as active state
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// Floating point registers
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// f32 values get... NaN-boxed into f64 values? wild
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// probably most efficiently treated like a union so can
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// do f32-native loads and stores and also update the top
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// bytes separately
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f: [f64; 32],
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// * fflags, accrued exceptions: bits 0-4
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// * nx: bit 0
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// * uf: bit 1
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// * of: bit 2
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// * dz: bit 3
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// * nv: bit 4
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// * frm, rounding mode: bits 5-7
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// * reserved: bits 8-31
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fcsr: i32,
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// When we add AOT and JIT, compiled functions will be
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// referenced in this lookup from PC to function pointer.
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// Because function references are linked separately on
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// each thread in WebAssembly, this has to live in each
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// core's state separately.
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executors: HashMap<i64, ExecutorFunc>,
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// Local dirty flags for JIT pages.
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// When we get a fence.i instructrion, look for all dirty
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// pages and invalidate any functions including them
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// Takes up to 1 byte per 4 KiB (1 MiB per 4 GiB) per thread.
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// Could be made more compact if only 1 bit is needed.
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dirty: Vec<u8>
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}
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impl CoreState {
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fn new(machine: &MachineState) -> Self {
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return Self {
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x: [
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0
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],
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f: [
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0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0,
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0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0,
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0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0,
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0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0
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],
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fcsr: 0,
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executors: HashMap::new(),
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dirty: vec![0u8; machine.memory.len()]
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}
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}
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}
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// R-type
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// * opcode: bits 0-6
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// * rd: bits 7-11
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// * funct3: bits 12-14
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// * rs1: bits 15-19
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// * rs2: bits 20-24
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// * func7: bits 25-31
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// I-type
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// * opcode: bits 0-6
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// * rd: bits 7-11
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// * funct3: bits 12-14
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// * rs1: bits 15-19
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// * imm[0:11]: bits 20-31
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// S-type
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// * opcode: bits 0-6
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// * imm[0:4]: bits 7-11
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// * funct3: bits 12-14
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// * rs1: bits 15-19
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// * rs2: bits 20-24
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// * imm[5:11]: bits 25-31
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// B-type
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// * opcode: bits 0-6
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// * imm[11]: bit 7
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// * imm[1:4]: bits 8-11
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// * funct3: bits 12-14
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// * rs1: bits 15-19
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// * rs2: bits 20-24
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// * imm[5:10]: bits 25-30
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// * imm[12]: bit 31
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// U-type
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// * opcode: bits 0-6
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// * rd: bits 7-11
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// * imm[12:31]
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// J-type
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// * opcode: bits 0-6
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// * rd: bits 7-11
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// * imm[12:19]: bits 12-19
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// * imm[11]: bit 20
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// * imm[1:10]: bits 21-30
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// * imm[20]: bit 31
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// sequential path is expected to be the common case on conditional branches
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// this aligns nicely with encoding forward to the next unconditional branch
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// but if possible unconditional jumps within a compilation unit may be doable
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// memory ordering instructions -- how can any of this be done? :D
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// FENCE.I could tell us to clear JIT caches :D
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extern "C" fn interpreter(
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_machine: *mut MachineState,
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_state: *mut CoreState,
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pc: i64) -> i64
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{
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println!("Hello, world!");
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return pc;
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}
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fn main() {
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let size = 8 * 1024 * 1024;
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let mut machine = MachineState::new(size);
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let mut core = CoreState::new(&machine);
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let pc = interpreter(&mut machine, &mut core, 0);
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println!("Ended with PC {}", pc);
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}
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