experimental wasm risc-v emulator stuff
| arg-test | ||
| hello | ||
| src | ||
| .gitignore | ||
| Cargo.lock | ||
| Cargo.toml | ||
| LICENSE.md | ||
| LORE.md | ||
| README.md | ||
Reliant
Experimental RISC-V emulator and JIT-compiler targeting WebAssembly. Copyright (C) 2025 by Brooke Vibber bvibber@pobox.com
Goals
- Learn more about RISC-V architecture and ISA
- Learn more about WebAssembly 2.0 by targeting a JIT compiler to current browser feature set
- Run simple static Linux binaries compiled for RV64GC in a web browser or node.js environment
- Support multiple cores with shared memory
Stretch goals
- emulate enough hardware interface to run a Linux kernel
Non-goals
- be commercially exploitable
- be a big popular project
- run arbitrary complex programs (eg kernel usermode emulation)
Licensing
Reliant is released under GPLv3 if you would like to experiment with it or derive further work from it; see LICENSING.md.