Save another few cycles per multiple
add_carry took a fixed 8 cycles with a lda/adc/sta pattern we can instead use bcc to handle the carry-not-set case in just 2 cycles, skipping over the inc which takes 5 cycles on the carry-is-set case. Result is 2-7 cycles instead of 8, saving 1-6 cycles twice per 16-bit multiplication or square. Neat!
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1 changed files with 18 additions and 16 deletions
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@ -435,11 +435,13 @@ input_max:
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add 4, dest, arg1, arg2
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.endmacro
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; 8 cycles
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; 2-7 cycles
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.macro add_carry dest
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lda dest ; 3 cyc
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adc #0 ; 2 cyc
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sta dest ; 3 cyc
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.scope
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bcc after ; 2 cyc
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inc dest ; 5 cyc
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after:
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.endscope
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.endmacro
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; 2 + 9 * byte cycles
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@ -771,10 +773,10 @@ inner_loop:
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.endproc
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; min base mem: 81 * 4 + 28 * 2 + 10 + 6 = 396 cyc
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; max base mem: 92 * 4 + 28 * 2 + 50 + 6 = 480 cyc
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; min ext-mem: 51 * 4 + 28 * 2 + 10 + 6 = 276 cyc
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; max ext-mem: 70 * 4 + 28 * 2 + 50 + 6 = 392 cyc
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; min base mem: 81 * 4 + 22 * 2 + 10 + 6 = 384 cyc
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; max base mem: 92 * 4 + 27 * 2 + 50 + 6 = 478 cyc
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; min ext-mem: 51 * 4 + 22 * 2 + 10 + 6 = 264 cyc
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; max ext-mem: 70 * 4 + 27 * 2 + 50 + 6 = 390 cyc
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.macro imul16_impl xe
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.local arg1
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.local arg2
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@ -798,11 +800,11 @@ inner_loop:
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imul8 inter, arg1 + 1, arg2, xe ; 81-92 or 51-70
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add16 result + 1, result + 1, inter ; 20 cyc
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add_carry result + 3 ; 8 cyc
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add_carry result + 3 ; 2-7 cyc
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imul8 inter, arg1, arg2 + 1, xe ; 81-92 or 51-70
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add16 result + 1, result + 1, inter ; 20 cyc
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add_carry result + 3 ; 8 cyc
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add_carry result + 3 ; 2-7 cyc
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; In case of negative inputs, adjust high word
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; https://stackoverflow.com/a/28827013
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@ -819,10 +821,10 @@ arg2_pos:
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rts ; 6 cyc
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.endmacro
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; min base ram: 5 + 19 * 2 + 81 + 28 * 2 + 6 = 186
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; max base ram: 23 + 19 * 2 + 92 + 28 * 2 + 6 = 215
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; min ext ram: 5 + 19 * 2 + 51 + 28 * 2 + 6 = 156
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; max ext ram: 23 + 19 * 2 + 70 + 28 * 2 + 6 = 193
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; min base ram: 5 + 19 * 2 + 81 + 22 * 2 + 6 = 174
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; max base ram: 23 + 19 * 2 + 92 + 27 * 2 + 6 = 213
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; min ext ram: 5 + 19 * 2 + 51 + 22 * 2 + 6 = 144
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; max ext ram: 23 + 19 * 2 + 70 + 27 * 2 + 6 = 191
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.macro sqr16_impl xe
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.scope
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arg = FR0 ; 16-bit arg (clobbered)
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@ -847,9 +849,9 @@ arg2_pos:
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imul8 inter, arg + 1, arg, xe ; 81-92 / 51-70 cyc
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add16 result + 1, result + 1, inter ; 20 cyc
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add_carry result + 3 ; 8 cyc
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add_carry result + 3 ; 2-7 cyc
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add16 result + 1, result + 1, inter ; 20 cyc
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add_carry result + 3 ; 8 cyc
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add_carry result + 3 ; 2-7 cyc
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rts ; 6 cyc
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.endscope
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