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experiment

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Brooke Vibber 2026-08-22 15:25:58 -07:00
commit 27995007c5
1 changed files with 11 additions and 13 deletions
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mandel-core.s
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@ -592,7 +592,7 @@ bank_switch_table:
.macro imul8 dest, arg1, arg2, xe
.if xe
; using 64KB lookup table
; 51-70 cycles
; 52-69 cycles
; clobbers x, y, dest, ptr
.scope
output = dest
@ -636,9 +636,7 @@ bank_switch_table:
txa ; 2 cyc
adc output ; 3 cyc
sta output ; 3 cyc
lda #0 ; 2 cyc
adc output+1 ; 3 cyc
sta output+1 ; 3 cyc
add_carry output + 1 ; 2-7 cyc
done:
.endscope
@ -775,8 +773,8 @@ inner_loop:
; min base mem: 81 * 4 + 22 * 2 + 10 + 6 = 384 cyc
; max base mem: 92 * 4 + 27 * 2 + 50 + 6 = 478 cyc
; min ext-mem: 51 * 4 + 22 * 2 + 10 + 6 = 264 cyc
; max ext-mem: 70 * 4 + 27 * 2 + 50 + 6 = 390 cyc
; min ext-mem: 52 * 4 + 22 * 2 + 10 + 6 = 268 cyc
; max ext-mem: 69 * 4 + 27 * 2 + 50 + 6 = 386 cyc
.macro imul16_impl xe
.local arg1
.local arg2
@ -794,15 +792,15 @@ inner_loop:
; h1*256*(h2*256 + l2) + l1*(h2*256 + l2)
; h1*h2*256*256 + h1*l2*256 + h2*l1*256 + l1*l2
imul8 result, arg1, arg2, xe ; 81-92 or 51-70
imul8 result, arg1, arg2, xe ; 81-92 or 52-69
imul8 result + 2, arg1 + 1, arg2 + 1, xe ; 81-92 or 51-70
imul8 result + 2, arg1 + 1, arg2 + 1, xe ; 81-92 or 52-69
imul8 inter, arg1 + 1, arg2, xe ; 81-92 or 51-70
imul8 inter, arg1 + 1, arg2, xe ; 81-92 or 52-69
add16 result + 1, result + 1, inter ; 20 cyc
add_carry result + 3 ; 2-7 cyc
imul8 inter, arg1, arg2 + 1, xe ; 81-92 or 51-70
imul8 inter, arg1, arg2 + 1, xe ; 81-92 or 52-69
add16 result + 1, result + 1, inter ; 20 cyc
add_carry result + 3 ; 2-7 cyc
@ -823,8 +821,8 @@ arg2_pos:
; min base ram: 5 + 19 * 2 + 81 + 22 * 2 + 6 = 174
; max base ram: 23 + 19 * 2 + 92 + 27 * 2 + 6 = 213
; min ext ram: 5 + 19 * 2 + 51 + 22 * 2 + 6 = 144
; max ext ram: 23 + 19 * 2 + 70 + 27 * 2 + 6 = 191
; min ext ram: 5 + 19 * 2 + 52 + 22 * 2 + 6 = 145
; max ext ram: 23 + 19 * 2 + 69 + 27 * 2 + 6 = 190
.macro sqr16_impl xe
.scope
arg = FR0 ; 16-bit arg (clobbered)
@ -847,7 +845,7 @@ arg2_pos:
sqr8 result + 2, arg + 1 ; 19 cyc
imul8 inter, arg + 1, arg, xe ; 81-92 / 51-70 cyc
imul8 inter, arg + 1, arg, xe ; 81-92 / 52-69 cyc
add16 result + 1, result + 1, inter ; 20 cyc
add_carry result + 3 ; 2-7 cyc
add16 result + 1, result + 1, inter ; 20 cyc